1. Field of the Invention
The invention relates generally to an input and output port circuit. More particularly, the invention relates to an input and output port circuit by which an output driving circuit can be simultaneously driven at a high voltage operation mode and a low voltage operation mode and the output driving circuit can be also selectively driven since they are also constructed in a multiple stage.
2. Description of the Prior Art
An input and output port circuit serves to output signals generated within a chip to the outside through an input/output pad or to transfer the signals inputted through the input/output pad to the chip.
Referring now to FIG. 1, a construction of a conventional input and output port circuit will be below described.
A two-input low voltage NAND gate 11 functions to logically combine a value of a signal register (SIGR) and a value of an input/output register (DIRR) that is inverted by an inverter I11. A two-input low voltage NOR gate 12 serves to logically combine the value of the signal register (SIGR) and the value of the input/output register (DIRR). At this time, the signal register (SIGR) stores output signals and the input/output register (DIRR) stores an input/output control signal for determining an input/output direction. A PMOS transistor P11 of a large size is connected between a low voltage (VDDL) output terminal (a logical value xe2x80x9c1xe2x80x9d) and a pad (PAD), thereby being driven depending on the output of the two-input low voltage NAND gate 11. A NMOS transistor N11 is connected between the pad (PAD) and the ground (GND) (a logical value xe2x80x9c0xe2x80x9d) and is also driven depending on the output of the two-input low voltage NOR gate 12. The PMOS transistor P11 and the NMOS transistor N11 are output driving transistors. Meanwhile, all of the circuits are constructed to perform a normal voltage operation.
A method of driving the conventional input and output port circuit constructed above will be described.
If the value of the input/output register (DIRR) is the logical value xe2x80x9c1xe2x80x9d (VDDL), the two-input low voltage NAND gate 11 outputs the logical value xe2x80x9c1xe2x80x9d (VDDL) and the two-input low voltage NOR gate 12 outputs the logical value xe2x80x9c0xe2x80x9d, regardless of the value of the signal register (SIGR). Therefore, the input signal is inputted by the input path, since both the transistors P11 and N11 are turned xe2x80x9cOFFxe2x80x9d by the outputs of the two-input low voltage NAND gate 11 and the two-input low voltage NOR gate 12, respectively.
Meanwhile, if the value of the input/output register (DIRR) is the logical value xe2x80x9c0xe2x80x9d, its output is determined depending on the value of the signal register (SIGR). If the value of the input/output register (DIRR) is the logical value xe2x80x9c0xe2x80x9d and the value of the signal register (SIGR) is the logical value xe2x80x9c1xe2x80x9d (VDDL), the two-input low voltage NAND gate 11 outputs the logical value xe2x80x9c0xe2x80x9d and the two-input low voltage NOR gate 12 also outputs the logical value xe2x80x9c0xe2x80x9d. As a result, the PMOS transistor P11 is turned xe2x80x9cONxe2x80x9d and the NMOS transistor N11 is turned xe2x80x9cOFFxe2x80x9d, so that the low voltage (VDDL) is outputted through the pad (PAD).
Further, if the value of the input/output register (DIRR) is the logical value xe2x80x9c0xe2x80x9d and the value of the signal register (SIGR) is the logical value xe2x80x9c0xe2x80x9d, the two-input low voltage NAND gate 11 outputs the logical value xe2x80x9c1xe2x80x9d (VDDL) and the two-input low voltage NOR gate 12 also outputs the logical value xe2x80x9c1xe2x80x9d (VDDL). As a result, the PMOS transistor P11 is turned xe2x80x9cOFFxe2x80x9d and the NMOS transistor N11 is turned xe2x80x9cONxe2x80x9d, so that the value of the ground (GND) is outputted through the pad (PAD).
It is required that the output driving transistor of the conventional input and output port circuit be constructed to have a very large size, in order to drive a load of a large capacitance. With this construction, a large amount of power consumption is required. In addition, in order to drive the high voltage, one additional input and output port circuit for use in the high voltage is required since the conventional output driving transistor is driven only at the low voltage.
The present invention is contrived to solve the above problems and an object of the present invention is to provide an input and output port circuit capable of simultaneously driving a high voltage and a low voltage using a single output driving circuit.
Another object of the present invention is to provide an input and output port circuit in which a single output driving circuit is constructed in a multiple stage and is thus selectively driven by an output control register, thus reducing the power consumption.
In order to accomplish the above object, the input and output port circuit according to the present invention, is characterized in that it comprises a signal register for storing output signals; an input/output register at which input/output control signals for determining an input/output direction are stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit connected to the signal register and the input/output register for determining the direction of a signal to be inputted or outputted through an input/output pad depending on a value of the signal register and a value of the input/output register, an output control circuit connected to the signal direction control circuit and the control register and driven depending on a value of the control register and output signals of the signal direction control circuit, and an output driving circuit connected to the output control circuit and the power supply switch circuit for outputting the low voltage, the high voltage or a ground value depending on the output signals of the signal direction control circuit and output signals of the output control circuit.
Furthermore, the input and output port circuit of the present invention comprises a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal that determines a normal voltage operation mode or a high voltage operation mode, a high voltage NAND gate for logically combining a value of a signal register and a value of an input/output register that is inverted by a first high voltage inverter, a high voltage NOR gate connected to the signal register and the input/output register for logically combining a value of the signal register and the value of the input/output register, a high voltage OR gate for logically combining an output of the high voltage NAND gate and a value of a control register that is inverted by a second high voltage inverter, a high voltage AND gate connected to the high voltage NOR gate and the control register for logically combining an output of the high voltage NOR gate and the value of the control register, and an output driving circuit connected between the power supply switch circuit and the around and constructed with a plurality of output driving circuits, wherein the output driving circuits are driven depending on output signals of the high voltage NAND gate, the high voltage NOR gate, the high voltage OR gate and the high voltage AND gate to output the low voltage, the high voltage or the ground value.